module multi_bit_full_adder (
	A, B,
	S, cout
);

parameter WIDTH = 4;

input [WIDTH - 1: 0] A;
input [WIDTH - 1: 0] B;

output reg [WIDTH - 1: 0] S;
output reg cout;

// Inner wiring for carry-in, a.k.a Ripple Carry Adding (RCA)
wire [WIDTH: 0] C;


assign C[0] = 0;
assign cout = C[WIDTH];

genvar i;
generate
	for (i = 0; i < WIDTH; i=i+1) begin
		single_bit_full_adder sbfa (.a(A[i]), .b(B[i]), .c(C[i]), .s(S[i]), .cout(C[i+1]));
	end
endgenerate


endmodule
